Pradeep appointed technical manager




Ausdia, the leading provider of design constraints and verification solutions that complement timing signoff for complex system-on-chip (SoC) designs from Sunnyvale, has expanded its regional offices in India to support increasing customer demand for the company’s flagship product TimevisionTM.

Pradeep CR has been appointed senior technical account manager at Ausdia’s new location in Bangalore, said the company in a release on 20 May 2019.

“We are very fortunate to have Pradeep, with his technical, regional and industry knowledge, join our team and support the needs of our customers,” said Sam Appleton, CEO, Ausdia.

“The expansion of our team reflects Ausdia’s commitment to our customers and our drive to address the continuing challenges of SoC designs,” he said.

Pradeep will support customers in the Asia Pac Rim region. As account manager, he will support customers pre-and post-sales. Prior to Ausdia, Pradeep was a staff applications consultant for Synopsys Design Methodology Solution (DMS) Products, chip-level static timing analysis (STA) lead at Microchip (Formerly PMC Sierra), lead application engineer at Extreme DA supporting GoldTime, field applications team supporting Mentor Graphics AMS suite (CoreEL Technologies) and Field Applications team supporting ASM assembly and fabrication product line.

Pradeep holds a bachelor’s degree in Electronics and Communications Engineering from Visvesvaraya Technological University and a master’s degree in VLSI System Design from Coventry University.

Silicon design is becoming vastly more complicated and costly, and harder to design and verify. This is due to raw design size, increasing use of IP blocks, advanced technology nodes, number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes.

Ausdia is an experienced, trusted technology company solving design’s toughest problems and transforming SoC design. The company is focused on delivering proven design constraint development and verification solutions that complement all implementation and timing signoff flows.


Please enter your comment!
Please enter your name here